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Simplified RAM timing "definitions" WIP
🕑 Added 2022-07-27 12:33:54 +0000 UTCRAM timings are how much time the RAM is given to complete various commands/operations. How quickly the RAM can complete a command/operation depends on the circuitry of the memory chip, the voltage it's running on and the temperature it's at. If you don't give the RAM chip enough time to complete a command you end up with missing/corrupted data. When you're lowering a timing you are merely trying to find the shortest amount of time in which the RAM chip can reliably complete whatever command/operation that timing governs. For example a good DDR4 Samsung 8Gb B-die chip at around 20-50C and 1.5V can complete a row activation in under 7.8ns but doesn't always mange it in under 7.5ns. Therefor setting the tRCD to 15 at 3800Mbps(1.9GHz) is stable as the row activation is given 7.89ns to finish (7.89 > 7.8). With a tRCD of 14 at 3800Mbps the row activation is given only 7.37ns which leads to errors as the row isn't always active by the time a read or write command is sent(7.37 < 7.5ns). For comparison DDR4 Samsung 8Gb C-die chip generally can't complete a row activation in less than 12ns regardless of operating voltage which limits it to a tRCD of 22 at 3600Mbps(1.8GHz)
tCL: clock cycles between a read command and the first bit of data being output by the memory chip
tCWL: clock cycles between a write command and first bit of data being sent to the memory chip
tRCD: clock cycles between a row activation command and read/write command (please note how tCL/tCWL is only relevant once a row is activated)
tRP: clock cycles to precharge(close/deactivate) a row
tRAS: minimum number of clock cycles between an activation and precharge command
command rate: number of clock cycles that a command is held on the CAD bus
tRRDS (dg): minimum clock cycles between activate commands to different bank groups
tRRDL (sg): minimum clock cycles between activate commands to the same bang group
tFAW: minimum number of clock cycles to send 4 activation commands
tRTP: minimum number of clock cycles between a read and precharge command
tWR: minimum number of clock cycles between the end of a write burst and a precharge command
tRFC: clock cycles given to the refresh cycle
tREFI: clock cycles between refresh cycles
Comments
Fahad AL-Sumaiti
Im glade its getting more serious and organized to get all this informations frome you. Great work 👏
Max Barnash
Glad to see you making information more accessible! Not sure if you’re planning this already, but notes on performance impact of settings would've been great as well.
